RISC-V International

RISC-V ISA Specifications

The canonical RISC-V Instruction Set Architecture specifications including the Unprivileged ISA (RV32I/RV64I base integer instructions) and Privileged Architecture specification. Freely available as ratified standards with a machine-readable database in the riscv-unified-db repo.

GitHub

Documentation

📖
Documentation
https://riscv.org/technical/specifications/

SDKs

📦
GitHubRepository
https://github.com/riscv/riscv-isa-manual
📦
GitHubRepository
https://github.com/riscv/riscv-unified-db

Other Resources

🔗
APIsJSON
https://raw.githubusercontent.com/api-evangelist/risc-v/refs/heads/main/apis.yml

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API entry from apis.yml

apis.yml Raw ↑ 
aid: risc-v:isa-specifications
name: RISC-V ISA Specifications
description: The canonical RISC-V Instruction Set Architecture specifications including the Unprivileged
  ISA (RV32I/RV64I base integer instructions) and Privileged Architecture specification. Freely available
  as ratified standards with a machine-readable database in the riscv-unified-db repo.
humanURL: https://riscv.org/technical/specifications/
tags:
- Instruction Set Architecture
- Privileged Architecture
- RISC-V
- Specifications
properties:
- type: Documentation
  url: https://riscv.org/technical/specifications/
- type: GitHubRepository
  url: https://github.com/riscv/riscv-isa-manual
- type: GitHubRepository
  url: https://github.com/riscv/riscv-unified-db