Cypress Semiconductor Rate Limits
Cypress' (now Infineon's) developer-facing surface is local: ModusToolbox tools, BSPs, HAL/PDL, AIROC, and CapSense libraries are compiled into firmware images that run on PSoC, AIROC, and TRAVEO silicon. There is no central HTTP API to throttle. Throughput is bounded by the underlying transport (UART, SPI, QSPI, USB, BLE, Wi-Fi) and the silicon's clock and sample rate, not by a vendor rate-limit policy. The only network-facing Infineon surfaces relevant to developers are the Infineon Developer Community forum and the GitHub-hosted documentation/release downloads, which inherit GitHub's standard rate limits rather than imposing a Cypress / Infineon policy.
Cypress Semiconductor Rate Limits is the machine-readable rate-limit profile for Cypress Semiconductor on the APIs.io network, conforming to the API Commons Rate Limits specification.
It captures 4 rate-limit definitions, measuring varies, bits-per-second, and requests.
The profile also includes 3 backoff/retry policies defined.
Tagged areas include Embedded Systems, Hardware, Infineon, and Rate Limiting.